Frequency searcher and frequency-locked data demodulator using a programmable rotator

ABSTRACT

A searcher is centered on frequency bins to search for an incoming signal. The frequency locked loop generates an initial phase signal and a phase increment signal that are input to an accumulator. The accumulator accumulates the phase increments over a predetermined interval. After the interval, the accumulator generates a control signal that instructs a rotator to perform a phase rotation function.

RELATED APPLICATIONS

[0001] This application claims the benefit of provisional U.S.application Serial No. 60/262,691, entitled “A METHOD FOR IMPROVEDREVERSE LINK CDMA SIGNAL ACQUISITION USING THE SEARCHER WITH N-PSK PHASEROTATOR FOR DOPPLER FREQUENCY COMPENSATION,” filed Jan. 19, 2001, whichis incorporated herein by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to communication systems.Particularly, the present invention relates to reverse link signalacquisition in a CDMA environment.

[0004] 2. Description of the Related Art

[0005] The radio frequency (RF) spectrum is a limited commodity. Only asmall portion of the spectrum can be assigned to each communicationsindustry. The assigned spectrum, therefore, must be used efficiently inorder to allow as many frequency users as possible to have access to thespectrum.

[0006] Multiple access modulation techniques are some of the mostefficient techniques for utilizing the RF spectrum. Examples of suchmodulation techniques include time division multiple access (TDMA),frequency division multiple access (FDMA), and code division multipleaccess (CDMA).

[0007] CDMA modulation employs a spectrum technique for the transmissionof information. The spread spectrum system uses a modulation techniquethat spreads the transmitted signal over a wide frequency band. Thisfrequency band is typically substantially wider than the minimumbandwidth required to transmit the signal. A signal having a bandwidthof only a few kilohertz can be spread over a bandwidth of more than amegahertz.

[0008] CDMA communications systems typically use directional antennaslocated in the center of a cell and broadcasting into sectors of thecell. The cells are located in major metropolitan areas, along highways,and along train tracks to allow consumers to communicate both at homeand while traveling.

[0009] All of the mobile telephones communicating in the CDMA systemtransmit on the same frequency. Therefore, in order for the base stationto identify each mobile, each mobile is assigned a unique pseudorandom(PN) spreading code that identifies that particular mobile to thesystem.

[0010] The mobile begins the registration process with a CDMA system bysending out a preamble signal that is comprised of chips. A base stationsearches for the preamble to determine if a mobile station is trying tocommunicate with the system. The base station may have to integrate overthousands of chips to find the mobile's preamble signal. This istypically not a problem if the preamble signal is at the properfrequency being searched by the base station.

[0011] Due to the Doppler effect, the critical cells are the cellslocated near highways or railway tracks. If a mobile is approaching abase station, the Doppler effect increases the signal's frequency asobserved by the base station. If the mobile is moving away from the basestation, the base station observes a signal having a frequency that isless than the frequency transmitted by the mobile. The amount offrequency shift is a function of the speed of the mobile.

[0012] The frequency of a signal transmitted by the mobile is alignedwith the local oscillator in the mobile. The base station's frequency issynchronized with the Global Positioning System. When the mobileacquires a signal from the base station, that signal's frequency will beoff. The mobile uses this shifted frequency to adjust its localoscillator in order to transmit back on the same frequency it hasreceived. The base station then receives a signal that is shifted againby the Doppler effect. The base station is therefore receiving a signalthat has double the frequency error. The two-way Doppler offsets may bein the range from 420 Hz for highway traffic to 1200 Hz for high-speedtrains.

[0013] A typical frequency searcher experiences difficulty finding thesignals transmitted by mobile telephones due to the double Dopplereffect. The double Doppler effect may reduce a mobile's signal as muchas 24 db below the threshold used by the searcher to find mobilesignals. There is a resulting need for a frequency searcher that iscapable of acquiring mobile signals that are affected by Doppler shift.

SUMMARY OF THE INVENTION

[0014] The present invention encompasses a searcher that finds andtracks the frequency of a received signal. The received signal typicallyis experiencing a phase error from the phase that for which the searcheris looking. The searcher comprises a frequency locked loop thatgenerates a phase increment signal in response to the detected phaseerror of the incoming signal. This phase error is used to generate aphase increment signal. An accumulator is coupled to the frequencylocked loop to accumulate the phase increments. After the accumulatorhas accumulated a predetermined phase increment, the accumulationgenerates a control signal to a programmable rotator. The programmablerotator performs a phase rotation function in response to the controlsignal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 shows a block diagram of the Frequency Locked Loop with theprogrammable rotator of the present invention.

[0016]FIG. 2 shows a flowchart of a programmable rotator process of thepresent invention.

[0017]FIG. 3 shows a table of segment lengths (in PN chips) and phaseincrements for different frequency bins.

[0018]FIG. 4 shows a plot of the probability of pilot signal detectionversus the frequency deviation in accordance with the programmablerotator of the present invention.

[0019]FIG. 5 shows a block diagram of a base station incorporating thesearcher with the programmable rotator of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020] The searcher of the present invention incorporating a FrequencyLocked Loop (FLL) with a programmable rotator eliminates the searchercoherent loss resulting from the Doppler effect. The present inventionprovides a significant improvement of the searcher sensitivity byreplacing a periodic 90° rotation with a programmable rotation ofmultiples of 45°. The searcher's performance is substantially equivalentto the searching technique known in the art as frequency binning.

[0021] In frequency binning, the intermediate frequency (IF) of thelocal oscillator adjusts the offset frequency control logic so that thebaseband signal is already corrected by the amount required. The amountof correction or offset by the local oscillator represents the binspacing.

[0022] However, in order to perform frequency binning, the hardwareneeds to introduce the frequency offset into the received signal. Thiscannot be done on a per mobile basis since all the mobiles are receivedtogether as a CDMA signal. Additionally, in cases when the frequency binoffset is introduced into the baseband signal, multiplication isgenerally required and the bit width of the datapath must increase. Thisincreases the hardware complexity in a non-linear fashion.

[0023] The searcher process of the present invention replaces thefrequency binning process by phase compensation or rotation that isapplied to the baseband I/Q samples. In the preferred embodiment, therotation is limited to multiples of 45° steps. Alternate embodiments useother rotation limits, such as 90° phase rotations.

[0024] The block diagram of FIG. 1 represents the searcher of thepresent invention, a FLL with hardware π/4 rotator. In the subsequentdiscussion of the present invention, each slot is divided into four512-chip intervals, subsequently referred to as “segments”. Each segmentis further divided into 8 “sub-segments” each having a length of 64chips. The pilot channel filtering is based on first accumulating thede-spread, hardware-rotated pilot chips over each segment and thensuitably combining the result over four segments, spanning an intervalof length 2048 chips.

[0025] Referring to FIG. 1, the preferred embodiment of the presentinvention is comprised of a rotator portion (101) together with a FLLportion (102). In the preferred embodiment, the rotator portion (101) isimplemented in hardware while the FLL portion (102) is implemented in adigital signal processor (DSP).

[0026] In general, the FLL rotates each segment-sum and inputs it to asliding window accumulator that sums its input over four segments. Theoutput of the sliding window accumulator is then de-rotated to generatean output of the pilot filter that is valid for a given segment. Therotation of segment sums is used to align the phase of the pilotaccumulated over each segment relative to one another. The de-rotationstep is performed in order to align the phase of the pilot filter outputwith the phase of the signal at the midpoint of the segment over whichthe pilot filter output is used for demodulation.

[0027] Referring to FIG. 1, the first step in pilot filtering is todecover the pilot channel from the hardware rotator output andaccumulate the result over each segment of 512 chips (105). Thedecovering operation is performed by the multiplier (126) that has thephase of the input signal, e^(j2πf) ^(_(n)) ^(T) ^(_(C)) , as one input.The phase signal is multiplied by the angle of rotation, e^(−JθR), fromthe hardware rotator (110). The generation of the angle of rotation isdiscussed subsequently.

[0028] The output of the multiplier (126) is the decovered pilot signalthat is input to a summer (105) for accumulation over 512 chips. Theaccumulated signal is multiplied with the local estimate of thefrequency error, e^(−jθL). The multiplier (130) output, e^(−jθ) ^(_(e))^([m]), is then input to a discriminator (110) to determine the crossproduct. The FLL is driven by the output of the cross product betweensuccessive 512 chip accumulations of the pilot signal. The output of thediscriminator (110) can be expressed as Gsin(δθ_(e)).

[0029] The output of the discriminator (110) is scaled by the “G” termto achieve the desired time constant/jitter variance. The cross productis applied to a loop filter (accumulator) (115) that is updated onceevery 512 chips. The output of the loop filter (115) provides theestimate, {circumflex over (f)}_(m), of the frequency offset.

[0030] The FLL also keeps track of the phase relationship betweendifferent segments by associating each segment with an average phase.This is accomplished by multiplying the estimate of the frequency offsetby 512 T_(C) (116). At high frequency offsets, the instantaneous phaseof the signal may vary considerably within each segment. The frequencyestimate generated by the loop filter defines the phase shift betweenone segment and the next. It also defines the difference in theinstantaneous phase of the signal from the beginning of the segment tothe end.

[0031] The estimate of the average phase of the segment is used by therotation and de-rotation of the pilot within the DSP portion (102). Thehardware rotator (110) uses the estimated phase difference to rotate thesignal within each segment so as to compensate for the change ininstantaneous signal phase over the segment.

[0032] The rotator (110) operates under the hypothesis that thedifference between the instantaneous phase of the signal and the averagephase of the signal over the given segment varies linearly with time. Itstarts with an initial value, δ radians, at the beginning of the segmentand ends with a final value of −δ radians at the end of the segment.With this assumption, the rotator (110) computes the average phase overeach sub-segment (64-chip interval), quantized to the nearest multipleof π/4 radians. The resulting rotation is applied to each sub-segment ofthe received signal, over the given segment. As a result, theinstantaneous phase of the signal at the output of the hardware rotator(110) remains nearly constant over each segment. The output of thehardware rotator (110) is used by the tracking loops, pilot filtering,and demodulation of a communications device.

[0033] The average phase of the signal over the segment is the same withor without the hardware rotator (110) of the present invention.Therefore, the hardware rotation process is transparent to pilotfiltering and demodulation. The hardware rotator (110), however,provides coherence gain by reducing the variance of the instantaneousphase within each segment. If the frequency offset is small, then thehardware rotator (110) provides no rotation, and the system degeneratesto the prior art implementation of a FLL.

[0034] In implementation, referring again to FIG. 1, the output of themultiplier (116) is input to an accumulator (117) that is updated every512 chips. The output of the accumulator (117) is the angle of rotation,θ_(L)[m], that is input to the DSP rotator (120) to generate the localestimate of the frequency error, e^(−jθL).

[0035] The outputs of the FLL can be expressed in x (initial phase) andy (phase increment) terms as follows:

x={−{circumflex over (f)} _(m)*(N/2 −32)T _(C)+π/8}mod 2π

y={circumflex over (f)} _(m)* 64T_(C)

[0036] where N is the coherent accumulation length that is 512 chips forFLL and demodulation. The x term is approximately equal to a negative ofhalf of the phase shift suffered by the received signal over the lengthof the segment. The “32” term is used to center the initial phase to thefirst sub-segment of length 64 chips. The additional π/8 term is used sothat the hardware needs to truncate, rather than round off, the value ofits state variable in order to determine the actual phase rotation. Inthe 8-bit scaling used to represent x, π/8 radians corresponds to thenumber 16.

[0037] The phase increment, y, represents the phase shift of the signalover a sub-segment (64-chip interval). The same phase parameters may beused for the demodulation of all RAKE receiver fingers, in acommunications device, associated with a given user.

[0038] During a frequency search, the above expressions for x and y aremodified slightly by replacing the frequency offset estimate,{circumflex over (f)}_(m), from the FLL with the frequency hypothesis,f_(H), and by setting N equal to the number of chips of coherentaccumulation used to compute the search energies. This results in x andy being expressed as:

x={−f _(H)*(N/2−32)T _(C)+π/8}mod 2π

y=f _(H)* 64T _(C).

[0039] During a search for frequencies of mobile communication devicesthat are already being tracked, the search, in an alternate embodiment,may be restricted to the single frequency hypothesis. This is thefrequency offset estimate that is closest to that estimated by the FLLfor that particular mobile.

[0040] The hardware rotator (110) of the present invention maintains an8-bit state variable whose value represents the phase angle at a highresolution of radians. In the preferred embodiment, this resolution isπ/128 radians. During a demodulation or search dispatch, the DSP portion(102) of the present invention programs the hardware rotator (110) witha 16-bit word that contains the two 8-bit parameters, x and y.

[0041] Referring again to FIG. 1, the 16-bit programming word isgenerated by the combination (150) of x that has been left shifted 8bits to truncate the 8-LSBs, and y. This combination is expressed as:

z=(x<<8)|y.

[0042] The higher significant byte of the 16-bit word contains theinitial value of the state variable, which determines the phase of therotator over the first sub-segment (64-chip interval). The lowersignificant byte of the 16-bit word contains the phase increment, whichdetermines the amount by which the state variable is incremented fromone sub-segment to the next. The phase accumulation is performed modulo256, which corresponds to a full rotation of 2π radians. The actualphase rotation for a given sub-segment is obtained by truncating the 5LSBs of the state variable, and multiplying the 3-bit result by π/4radians.

[0043] During demodulation dispatches, the initial phase and phaseincrement are computed from an the estimated of the frequency offsetprovided by the FLL, and the length of the segment (N=512 chips).

[0044] The x and y outputs of the FLL are input to the rotator portion(101) of the present invention. The rotator portion (101) is initializedby the initial phase (x) from the FLL. The phase increment (y) is inputto a modulo 256 accumulator (140) that is updated at a 64-chip rate.Both the x and y inputs are 8 bits in width.

[0045] The output of the 8-bit accumulator (140) is input to a shiftregister (125) or other shifting device that shifts the accumulatedsignal by five places to the right. This generates a three remaining bitsignal (R=R₂R₁R₀) that is input to the hardware rotator (110) of thepresent invention. These are the bits that are applied to the hardwarerotator (110) that instruct the rotator to perform the phase rotation apredetermined amount. For example, in one embodiment, R=001 (R₂=0, R₁=0,R₀=1) would instruct the rotator to rotate by π/4.

[0046] The hardware rotator (110) in the rotator portion (101) minimizesthe coherence loss in the presence of large frequency offsets betweenthe reverse link signal, received by the base station, and the localoscillator. This is achieved by phase shifting the signal by a(possibly) different amount during each 64-chip sub-segment. In thisway, the instantaneous phase of the signal remains close to the averagephase of the signal over each segment.

[0047] The hardware rotator (110) applies phase shifts to the despreadsignal (112), e^(j2πf) ^(_(n)) ^(T) ^(_(C)) , at the chip rate, prior topilot filtering and demodulation that is performed by the DSP portion(102). The angle of rotation, in the preferred embodiment, is a multipleof 45° and the angle is kept constant over each sub-segment (64 chips).

[0048]FIG. 2 illustrates a flowchart of a searcher process in accordancewith the programmable rotator of the present invention. The processbegins by centering the searcher on the expected frequency bins (step201). The expected frequency bin is different for different applicationsand locations of base stations that incorporate the searcher of thepresent invention. For example, if the base station is located on ahighway, the searcher may be centered on frequency bins +400 Hz and −400Hz. If the base station is located on a railway, the frequency bins maybe +1200 Hz and −1200 Hz, depending on the expected speeds of thetrains.

[0049] The base station receives the pilot signal and decovers it (step205). The decovering process is well known in the art and is notdiscussed further.

[0050] The FLL of the present invention then determines the phase errorpresent in the signal (step 210). This error is determined after a64-chip interval as described above. Alternate embodiments use otherintervals of chip lengths.

[0051] The phase error is accumulated until it has reached apredetermined accumulated error (step 215). In the preferred embodiment,the predetermined accumulated error threshold is 45. For example, ifafter every 64-chip interval the error is 6°, this error is accumulateduntil the total error reaches 45°. If the accumulated error has reachedthe predetermined accumulated error threshold (step 220), the rotationis performed (step 225) as described above. If the threshold has notbeen reached (step 220), the process goes back to receiving andaccumulating the phase errors (steps 205-220) until the threshold isreached.

[0052] After the rotation is performed (step 225), the accumulated phaseerror is reset to zero (step 230). The process then continues thetracking by returning to the receiving step (step 205) and repeating.

[0053] In an alternate embodiment, the same 8-PSK rotator can be usedfor both the FLL and the searcher. The rotator control in the searcherneeds to be separated from the phase estimate output by the FLL.Instead, the value of the phase needs to be overwritten by the DSP andhas to be interfaced to a higher layer of the software that implementsthe searcher process.

[0054] By supplying the phase increment, the DSP controls the point atwhich the rotator phase actually switches. The phase update is enabledevery 64-chips.

[0055] The DSP of the preferred embodiment is limited to an 8-bit phaserepresentation. Thus, the desired phase increments need to be quantizedto be represented by an 8-bit integer number. This computation onlyconcerns a 45° rotator since it is the preferred embodiment. Thecomputations for a QPSK rotator would be different.

[0056] There is a tradeoff between optimal bin placement and hardwaresimplification and optimization. The general rule in choosing the phaserotator segment in chips, denoted as L, was minimizing the Mean lossfunction and Max loss function over the specified Doppler range. For aspecified searcher mode (e.g., 3-Bin 45°), the L is a function of range.For example, L=464 is optimal for the F_(d)=±400 Hz range, but L=272 isoptimal for the range of ±800 Hz. The definition of range is arbitraryand does not have to be strict. One can assume that L=448 will be anoptimal L value for some range just above ±400 Hz and well below ±800Hz.

[0057] Using this approach, we can derive phase increment values togenerate a value close to an appropriate L. The procedure for computinginteger Phase increment (θ) is expressed as:

(L/64) θ=256/8,

[0058] where 256 is the 8-bit representation of a full 360° phase, and256/8 is the representation of 45°. Thus, θ=256*8/L can be used tocompute θ increments for the DSP. FIG. 3 illustrates the phaseincrements in LSBs and the corresponding L, in PN chips, using thisalternate embodiment approach.

[0059] In the embodiment where the FLL and searcher share the rotatordesign, the knowledge of frequency can be shared between these twoblocks. During the initial acquisition, if the searcher signal is foundin one of the frequency bins, this bin center can be used to initializethe FLL. Similarly, when performing set maintenance searches, thesearcher can be programmed to search only one frequency bincorresponding to the offset value in the FLL accumulator.

[0060]FIG. 4 illustrates a plot of the probability of pilot signaldetection versus the frequency deviation of the pilot signal. This plotshows a comparison between the probability of detecting the pilot signalusing a searcher without a rotator and a searcher using the programmablerotator of the present invention.

[0061] Both plots assume that EcNt=−18 dB, number of chips (Nc)=1024,and the number of non-coherent accumulations (Nn)=6. Additionally, therotator used in the plot is a 2-bin, 45° rotator.

[0062] Referring to FIG. 4, it can be seen that the probability of asearcher without a rotator (401) detecting the pilot is substantiallyless than a searcher with the rotator (402) of the present invention.This is especially true when the pilot is experiencing a ±400 Hz or moreof a Doppler shift.

[0063]FIG. 5 illustrates a block diagram of a base station incorporatingthe searcher of the present invention. The base station is comprised ofa transmitter (501) that modulates and transmits signals over an airchannel using the antenna (502). The transmitter gets its signals to bemodulated and transmitted from the network that is coupled to the basestation. This network can be a cellular infrastructure network, thepublic switched telephone network, or any other network requiringconnection to a wireless base station.

[0064] The antenna (502) also receives signals from mobile communicationdevices. These signals are coupled to the receiver (505) of the basestation for demodulation and transmission to the network. The receiver(505) comprises the searcher incorporating the FLL and programmablerotator of the present invention.

[0065] The base station is further comprised of a base stationcontroller (510). The controller (510) is responsible for control of thebase station's transmitter, receiver, and other components not shown butare well known in the art.

[0066] In summary, the searcher of the present invention can specify anarbitrary number of frequency bins and perform frequency as well as codespace searching. By using a programmable rotator, the searcher is ableto find and track a signal that has a large frequency error, such asthose experiencing a Doppler effect caused by movement away from andtowards the base station.

We claim:
 1. A searcher for finding the frequency of a received signal comprising a phase error, the searcher comprising: a frequency locked loop that generates a phase increment signal in response to the phase error of the received signal; and a programmable rotator coupled to the frequency locked loop, the programmable rotator performing a phase rotation function in response to the phase increment signal.
 2. The searcher of claim 1 wherein the programmable rotator is an 8-Phase Shift Keying rotator.
 3. The searcher of claim 1 wherein the programmable rotator is a Quadrature Phase Shift Keying rotator.
 4. The searcher of claim 1 and further including a phase error accumulator coupled to the phase error signal, the phase error accumulator accumulating phase error signals from the frequency locked loop and generating a control signal that instructs the programmable rotator to perform the phase rotation function.
 5. The searcher of claim 4 and further including a shift register coupled between the phase error accumulator and the programmable rotator, the shift register truncating a predetermined number of bits of the control signal.
 6. A searcher for finding the frequency of a received signal comprising a phase error, the searcher comprising: a frequency locked loop that generates a phase increment signal in response to the phase error of the received signal; a phase error accumulator coupled to the frequency locked loop, the phase error accumulator accumulating a plurality of phase increment signals and generating a control signal in response to the accumulated phase increment signals; and an 8-Phase Shift Keying programmable rotator coupled to the phase error accumulator, rotator performing a phase rotation function in response to the control signal.
 7. The searcher of claim 6 and further including a shift register apparatus coupled between the rotator and the phase error accumulator, the shift register apparatus shifting bits of the control signal a predetermined amount in order to truncate the control signal to a predetermined number of bits.
 8. The searcher of claim 6 wherein the phase error accumulator accumulates phase increment signals over a 64-chip interval.
 9. The searcher of claim 6 wherein the frequency locked loop further comprises means for generating an initial phase signal that is coupled to the 8-Phase Shift Keying programmable rotator and initializes the rotator to a predetermined starting phase.
 10. A searcher for finding the frequency of a received signal comprising a phase error, the searcher comprising: a frequency locked loop that generates a phase increment signal in response to the phase error of the received signal; a phase error accumulator coupled to the frequency locked loop, the phase error accumulator accumulating a plurality of phase increment signals and generating a control signal in response to the accumulated phase increment signals; and a Quadrature Phase Shift Keying programmable rotator coupled to the phase error accumulator, rotator performing a phase rotation function in response to the control signal.
 11. The searcher of claim 10 and further including a shift register apparatus coupled between the rotator and the phase error accumulator, the shift register apparatus shifting bits of the control signal a predetermined amount in order to truncate the control signal to a predetermined number of bits.
 12. The searcher of claim 10 wherein the phase error accumulator accumulates phase increment signals over a 64-chip interval.
 13. The searcher of claim 10 wherein the frequency locked loop further comprises means for generating an initial phase signal that is coupled to the Quadrature Phase Shift Keying programmable rotator and initializes the rotator to a predetermined starting phase.
 14. A searcher method for finding a signal having a frequency deviation from an expected frequency, the method comprising the steps of: initializing the searcher on predetermined frequency bins; determining a phase error in the signal; generating a phase increment in response to the phase error; accumulating the phase increments to generate a total phase increment; and when the total phase increment has reached a predetermined total phase increment threshold, performing a phase rotation function that is substantially equivalent to the total phase increment.
 15. The method of claim 14 and further including the step of resetting the accumulated phase increments after performing the phase rotation function.
 16. The method of claim 14 wherein the phase rotation function is a Quadrature Phase Shift Keying function.
 17. The method of claim 14 wherein the phase rotation function is an 8-Phase Shift Keying function.
 18. The method of claim 14 wherein the total phase increment threshold is substantially equivalent to π/4 radians.
 19. The method of claim 14 wherein the total phase increment threshold is substantially equivalent to π/2 radians.
 20. A base station that communicates with wireless mobile stations, the base station comprising: a transmitter that modulates and transmits signals from a network; and a receiver that receives and demodulates received signals, the receiver comprising a searcher that finds the frequency of the received signal, the frequency having a phase error, the searcher comprising: a frequency locked loop that generates a phase increment signal in response to the phase error of the received signal; a phase error accumulator coupled to the frequency locked loop, the phase error accumulator accumulating a plurality of phase increment signals to generate a total accumulated phase increment, the phase error accumulator generating a control signal in response to the total accumulated phase increment; and a programmable rotator coupled to the phase error accumulator, rotator performing a phase rotation function in response to the control signal.
 21. The base station of claim 20 wherein the programmable rotator is a Quadrature Phase Shift Keying rotator.
 22. The base station of claim 20 wherein the programmable rotator is a 8-Phase Shift Keying rotator.
 23. The base station of claim 20 wherein the total accumulated phase increment is π/4 radians.
 24. The base station of claim 20 wherein the total accumulated phase increment is π/2 radians. 